1. Field of the Invention
This invention relates to the field of digital electronics, and more particularly to digital logic implementations in programmable logic devices such as field programmable gate arrays (FPGAs).
2. Description of the Background Art
In the construction of electronic circuits, many designers use programmable logic devices such as FPGAs to implement digital circuit designs. One commonly-known FPGA is the Xilinx XC4000.TM. Series device, which is described on pages 4-5 through 4-78 of the Xilinx 1996 Data Book entitled "The Programmable Logic Data Book" (hereinafter referred to as "the Xilinx Data Book"), published September, 1996, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.)
Using a programmable logic device can reduce the amount of time between the conception of a circuit design and the production of a working circuit prototype, as well as facilitating later design changes. However, the utility of a programmable logic device for implementing large and/or complex logic functions may be limited by a lack of appropriate logic circuitry. Specifically, the number of drivers that may be supported on a single line or bus is typically limited by a fixed number of tristate buffers in the device architecture. This problem may be more clearly understood with reference to FIG. 1, which shows a simplified version of the Xilinx XC4000 Series FPGA architecture.
An FPGA typically comprises programmable logic blocks and programmable interconnect mechanisms for interconnecting the blocks. The FPGA of FIG. 1 includes a central array of Configurable Logic Blocks (CLBs) comprising function generators, registers, and so forth, surrounded by a ring of Input/Output Blocks (IOBs). Programmable interconnect lines of various lengths (not shown except for horizonal long lines) provide interconnections between the various CLBs and IOBs. Horizontal long lines are provided that span the device between the rows of CLBs. Each long line is accessible both from each CLB in the associated row and from the IOBs situated at each end of the row. Each row of CLBs has two associated long lines, one above and one below the row of CLBs. The long line drivers are implemented using tristate buffers, shown as diamond shapes in FIG. 1. The long lines are commonly used to implement busses in the FPGA, and the number of drivers on the bus is therefore limited by the number of tristate buffers along the horizontal long line. In the FPGA of FIG. 1, the maximum number of drivers on a long line is equal to the number of CLBs in the row plus two for the IOBs.
The tristate buffers are more clearly shown in FIG. 2, which is a detailed block diagram of a single row of CLBs and associated long lines from the FPGA architecture of FIG. 1. (An FPGA typically comprises many more than four CLBs per row, but only four are shown in the figures herein in order to simplify the drawings.) Each tristate buffer (206-213) has a data input, a tristate input (T206-T213), and an output that drives a long line (200, 201). Each tristate buffer is programmable and may assume any of several states, as described on pages 4-29 to 4-30 of the Xilinx Data Book. To avoid contention on long line 200, only one tristate buffer on each long line should be enabled at a given time.
In FIG. 2, CLBs 202, 203, 204, 205 are coupled to long line 200 via tristate buffers 206, 207, 208, 209, respectively. CLBs 202, 203, 204, 205 are further coupled to long line 201 via tristate buffers 210, 211, 212, 213, respectively.
When implementing a bus having a plurality of signal lines (bit lines), typically one long line is used for each bit line. In the circuit of FIG. 2, for example, long lines 200 and 201 can be configured to implement a two-bit bus with four bus drivers, wherein long line 200 carries a first bit and long line 201 carries a second bit of the bus signal.
In summary, in the FPGA of FIGS. 1 and 2, as well as in other programmable logic devices, the number of tristate buffers associated with any one long line is fixed, placing a maximum on the number of drivers that can drive each long line. The utility of the device in applications having a large number of drivers driving a common line or bus is diminished once this tristate buffer limit is reached. No mechanism is provided in the prior art for implementing tristate buffer driven lines having an arbitrarily large number of driver inputs.
A related problem is the implementation of functions with a large numbers of inputs ("wide logic functions"). While logic functions are typically implemented in CLBs, the number of inputs is limited. For example, functions with up to nine inputs can be supported by a single Xilinx XC4000 Series CLB. To calculate functions with more than nine inputs, additional CLBs must be used and cascaded together. This cascading introduces additional block delays into the circuit. Another disadvantage to using CLBs to implement wide logic functions is that all of the inputs must be brought to the CLBs, introducing interconnect delay and producing interconnect congestion that can make the resulting circuit unroutable. Therefore, it is commonly known to use long lines to implement wide functions, using a technique known as "wired logic", or "wired AND functions". (Such logic, for example, is shown and discussed in pages 3-5 through 3-11 of the Xilinx Data Book, which pages are incorporated herein by reference.) However, the number of inputs to a wired logic function is limited by the number of tristate buffers along the long line. It is desirable to provide a structure for generating wide functions of an arbitrary width.